Re-synchronization or clock adjustment may be needed for various systems, or for the interfaces between various systems. Video systems in particular may benefit from timing adjustment. More recently, 3D conversion of video content is performed on various devices, such as a handheld, headset display, or a larger display system. Such devices may use a System-On-a-Chip (SOC) to convert video streams by adjusting or tuning various clocks.
Even when clocks are synchronized to the same frequency, data may be mis-clocked. FIG. 1 is a waveform diagram of tuning a clock to correct for a duty-cycle error. The falling edge of CLK causes both DATA 1 and DATA 2 to change state. However, DATA1 is much faster than DATA2, such as due to differences in propagation delays in a circuit. Both DATA1 and DATA2 are sampled, latched, or clocked in on the rising edge of CLK. DATA1 is faster to become stable, allowing BIT11, BIT12, and BIT13 to be sampled at successive rising edges of CLK.
However, the longer propagation delay for DATA2 causes its data BIT21, BIT22, to become stable after the rising edge of CLK. If CLK were used to sample DATA2, the wrong data could be captured. A synchronization failure would occur.
The clock can be tuned to allow more time for slower signals to finish propagation. The clock frequency is held constant, but the duty cycle is adjusted. In this example, the rising edge of CLK is delayed while the rising edge of CLK is held constant. The resulting tuned clock TUNED CLK has the same frequency and period of CLK, but has a smaller duty cycle. The rising edge of CLK is delayed by time T to generate TUNED CLK. The delayed rising clock edge of TUNED CLK allows more time for DATA2 to propagate and become stable, so that BIT21 and BIT22 are successfully captured by TUNED CLK but not by CLK.
The longer delay of DATA2 may be due to actual signal propagation paths that generate DATA2, or may be due to signal timings generated by another system, such as a video stream with skewed timing. Such timing variances can be compensated for by tuning the duty cycle.
A tuned clock with an adjustable duty cycle can be generated with an integrator. FIG. 2 is a waveform diagram of an integrator adjusting the duty cycle to generate a tuned clock. An integrator can have a charge pump that charges and discharges a capacitor to generate a triangle wave. The INTEGRATOR waveform is a triangle wave. A voltage threshold THRESHOLD can be set and compared to the triangle wave. When the triangle waveform is above the threshold, then the output is driven high; otherwise the output is driven low. The resulting output OUT has the same frequency set by the integrator, but the duty cycle can be adjusted by adjusting the voltage of the threshold. Lowering the threshold causes the duty cycle to increase since more of the triangle wave is above the threshold, resulting in a longer high pulse for the output OUT.
While using an integrator to adjust the duty cycle is useful, integrators often are quite sensitive to variations in temperature, supply voltage, and manufacturing process. This sensitivity can degrade the precision of any resulting tuned clock. As a system heats up during operation, or as the power supply fluctuates due to varying loading, the resulting tuned clock can drift and no longer have its clock edge in the correctly timed position. Synchronization failures can re-appear.
What is desired is a clock generator with an adjustable duty cycle. A duty-cycle controller that adjusts the duty cycle of a clock is desirable. A calibration circuit that calibrates a configuration of the duty cycle controller is desirable to more precisely adjust the duty cycle.